Aspects of semiconductor technology have focused on obtaining semiconductor devices having high speed and high integration. Such high speed and high integration requirements may be achieved through the fineness of a pattern roll. Light exposure may be approaching its limitation of essential resolution due to the wavelength of exposure. In light exposure using g-line (436 nm) or i-line (365 nm) as a light source, generally, the pattern role has a limitation of 0.5 μm. The degree of integration of a semiconductor device fabricating using such a pattern role corresponds to a 16 M bit DRAM. However, since mass production of large scale integration (LSI) has been achieved using this step, the development of enhanced fineness technology may be required.
Far ultraviolet lithography may be used as fine processing technology, and can implement 0.2 to 0.4 μm processing. In the case of using resist material having a low light absorption, far ultraviolet lithography can be used to form a pattern having a side wall almost substantially perpendicular to a substrate. Recently, a technology using KrF excimer laser having high brightness using far ultraviolet as a light source has been employed.
As semiconductor devices become highly integrated, methods reducing the sizes of a device isolating region and a device forming region, particularly, an active region among several methods has been proposed.
In a process for fabricating an integrated circuit, a transistor, a liquid crystal or a diode, etc., a photolithographic process for forming a fine pattern and/or an etching process for forming an electrode pattern connected thereto may be used. For example, when forming a desired pattern of a semiconductor layer on and/or over a semiconductor substrate, an insulation layer, a wiring layer, etc. may first be formed on and/or over the semiconductor substrate. After conducting a cleaning process, a photoresist suitable for the pattern may then be coated using a coating method such as a spin coat, a spray coat, a deep coat, etc. When enhanced stability and uniformity are required, a spin coat may be performed by chucking a wafer in a vacuum and rapidly rotating the wafer.
Next, a photo mask corresponding to a desired pattern may be arranged on and/or over the photoresist and ultraviolet light is irradiated thereto, thereby performing an exposure process. Thereafter, a desired resist pattern may be formed using a development process such as wetting or spraying. It may be difficult to manage temperature, density, aging, etc. using wetting, and may be relatively easy to manage such factors using spraying. An apparatus making in-line using a spray process may be used. The layer may be selectively removed using the photoresist pattern as a mask, thereby making it possible to form a desired pattern.
As illustrated in example FIG. 1A, etch material 30 such as an isolation layer or a metal layer may be formed on and/or over semiconductor substrate 20. A plurality if photoresists 40 may be coated on and/or over etch material 30 and then selectively patterned using exposure and development processes to define a pattern forming region.
As illustrated in example FIG. 1B, the exposed etch material 30 may be selectively removed using patterned photoresist 40 as a mask to form a plurality of material patterns 30a. 
As illustrated in example FIG. 1C, photoresist 40 may then be removed, and a cleaning process may be performed with respect to semiconductor substrate 20 to remove foreign material, debris and the like generated in the etching process.
A photolithographic process using a light source such as ArF, KrF, F2 and the like and the patterned photoresist has several limitations in implementing a fine pattern such as a gate. It may be difficult to implement the line width of several nm in magnitude due to the limitation of an optical system and the limitation of resolution of the photoresist polymer itself.